The present invention pertains to a method for forming interconnections on semiconductor integrated circuit chips. In particular, the present invention pertains to a method for the etchback of a conductive material during a semiconductor manufacturing process.
Since the development of the first integrated circuit device, the technology of semiconductor fabrication has focused on minimizing the feature size of semiconductor devices. With the advancements made in processing technologies such as deposition, lithography, etching, and thermal treatment, the packing density of integrated circuit chips has greatly increased. A single chip manufactured using the present semiconductor fabrication technology may include millions or even billions of devices such as transistors and capacitors. To accomplish this, the feature size of integrated circuit devices has been scaled down to a submicron level.
When semiconductor devices are densely arranged on an integrated circuit chip, the conductive interconnections between such devices must be scaled down accordingly. All of the conductive pathways (typically, polysilicon or metal connections) between devices must be scaled down in width, without degrading the operating characteristics of the integrated circuit. When used to connect submicron size devices, the interconnections must provide defect-free contact between conducting and connecting members.
The interconnections on integrated circuit chips are generally constructed to have several layers of metal pathways. With the increased packing density of modern semiconductor chips, three or more layers of metal connections are commonly used for constructing the entire circuit. The connections between metal layers and underlying conductive regions of polysilicon are provided by means of conductive plugs. FIG. 1 shows a semiconductor structure 100 which includes a semiconductor substrate 110 having a conductive region 112 to be electrically connected with other conductive regions in structure 100. A dielectric layer 114 is formed over the substrate 110 and subsequently pattern etched to define a contact hole 115 therein. After the deposition of a conductive wetting layer 116 and a conductive diffusion barrier layer 118, a filling layer 120 of a conductive material is deposited into the contact hole 115 for the purpose of forming a contact plug 122, which provides an electrical connection to conductive region 112.
As shown in FIG. 2, the filling layer 120 is then etched back so that the contact plug remains in the contact hole 115 for the purpose of making a conductive connection with o an overlying metal layer deposited in a subsequent processing step. Ideally, the filling layer 120 is etched back until the portion of conductive material outside the contact hole 115 is removed and the portion inside the contact hole 115 remains (i.e., the top surface of the portion of the filling layer remaining within the contact hole is even with the top surface of the dielectric layer 114).
A conventional method of filling a contact hole is to deposit a layer of metal over dielectric layer 114 and then to etchback the metal layer to create a xe2x80x9cplugxe2x80x9d in the hole. For example, and not by way of limitation, the metal may be tungsten, aluminum, aluminum 18 copper, aluminum-silicon-copper, or aluminum-silicon. Regardless of the conductive material used, it is difficult to control the etchback process so that the conductive residue is completely removed from the upper surface of the dielectric layer, while leaving the contact hole completely filled with conductive material. If the etchback process is performed until the conductive residues 222 (shown in FIG. 2) are completely removed, plug loss is found to result in a shortened contact plug 224. By contrast, an etchback process without plug loss may result in a significant amount of residue remaining outside the contact hole. The remaining residues 222 may create undesired current leakage or short-circuiting problems in the final product.
In their paper entitled xe2x80x9cTungsten Etch Technology for Submicron Devicesxe2x80x9d (Advanced Metallization for ULSI Applications Proceedings of Conference, pp. 463-469, 1992), Ivo Miller et al. disclosed the above problem in a tungsten etchback process. Miller et al. describe that, in a blanket deposition/etchback scheme, the primary objective is to leave a via or contact completely filled with tungsten. However, the problem of microloading (a change in the local etch rate relative to the location of the material being etched on the substrate) is of paramount importance, and the paper presents detailed descriptions of a method for reducing the microloading effect. Extensive work was performed in an attempt to minimize the effect of microloading by introducing polymerizing chemistries at endpoint and by reducing etchant concentration. However, Miller et al. point out that these approaches also have an impact on system cleanliness and on wafer throughput. Miller et al. developed and characterized a fluorine-based tungsten etchback process for a single wafer plasma etch system. The effects of temperature on the microloading effect and on the etch selectivity toward tungsten relative to titanium nitride were evaluated and summarized. Although the mechanism was not discussed in detail, Miller et al. found that control of the processing temperature assists in controlling tungsten plug loss and tungsten: titanium nitride etch selectivity. Miller et al. proposed a method for controlling the microloading effect and the tungsten to titanium nitride etch selectivity using a reduced processing temperature, allowing optimum process latitude without excessive tungsten plug or titanium nitride barrier layer loss.
U.S. Pat. No. 5,641,710, issued Jun. 24, 1997, to Wang et al., discloses a tungsten etchback process with an accompanying annealing process. A post-reactive ion etch (RIE) anneal is performed in a nitrogen ambient to remove moisture from the surrounding dielectric layers of plugs and also to form a protective, nitrogen-containing tungsten layer to fill the crevice in the tungsten plug. However, Wang et al. does not address the plug loss problem in tungsten etchback processes.
The present invention relates to a method of reducing or eliminating the problem of plug loss during the etchback of a conductive plug, while simultaneously enabling the removal of residual conductive material present on adjacent surfaces after deposition of the conductive plug. The method leaves essentially undisturbed conductive material residing in a cavity within the substrate, while the conductive material is removed from the substrate surface (despite the presence of an opening to the cavity from the surface of the substrate).
A typical beginning structure for performing the method of the invention comprises a substrate containing a number of cavities, such as contact vias, and may also contain interconnect trenches. Blanket deposition of a conductive material over the substrate fills the cavities and leaves a continuous layer of conductive material over the substrate surface. The conductive material may be tungsten, or another metal such as aluminum-copper, aluminum-silicon-copper, or aluminum silicon, by way of example and not by way of limitation.
In a preferred embodiment method of the invention, the conductive material is tungsten. Typically, the tungsten is not deposited directly upon a dielectric layer surface. Rather, the dielectric layer surface, including openings and cavities within the dielectric layer, is first covered with a wetting layer, such as, for example, titanium, followed by a diffusion barrier layer, such as, for example, titanium nitride, followed by deposition of be tungsten.
According to the method of the invention, a first, rapid etchback process is typically performed, using a fluorine-comprising etch techniques known in the art known to provide a good etch rate, for the purpose of removing most of the conductive material from the surface of the substrate. For example, and not by way of limitation, the first etchback step may be performed using a plasma generated from a fluorine-comprising gas (preferably, SF6) and argon. The plasma source gas may further contain additional gases such as oxygen or nitrogen (where nitrogen is used to replace at least a portion of the argon). The initial substrate temperature is typically within the range of about 10xc2x0 C. to about 20xc2x0 C., and is raised so that it ranges from about 40xc2x0 C. to about 60xc2x0 C., during the first etchback step.
Subsequently, a buffer (i.e., transition) step is performed during which either the plasma source power or the substrate bias power, or both, are significantly reduced or discontinued, and the substrate surface temperature is decreased, typically, by at least 10xc2x0 C., to a temperature of less than about 40xc2x0 C., for example and not by way of limitation. This enables precise control of the etch rate and alters the selectivity so that the etch rate of tungsten is reduced relative to the adjacent diffusion barrier of titanium nitride. As an example, and not by way of limitation, the substrate bias power may be reduced to 50% or less of the substrate bias power used in the first etchback step. Alternatively, both the plasma source power and the substrate bias power may be turned off during the performance of the buffer step. If necessary, the substrate support electrode on which the substrate rests may be cooled so that the substrate temperature will fall within the desired temperature range.
A second etchback step is then performed to remove residual conductive material from the substrate surface, while leaving essentially undisturbed conductive material residing in the cavities. The second etchback step is conducted using a modified etch chemistry, where the flow rate of the fluorine-comprising gas is preferably reduced by about 50%, and the flow rate of argon is preferably doubled, relative to the flow rates used in the first etch step. During the performance of the second etchback step, the substrate temperature is typically maintained at the reduced temperature achieved in the buffer step, for example, at a temperature of less than about 40xc2x0 C. If necessary, the substrate may be cooled by cooling the substrate support pedestal (electrode) upon which the substrate rests. The plasma source power and substrate bias power are preferably increased to at least 50% of that used in the first etch step.
We have discovered that the etching rate of residues located on the substrate surface outside a contact hole (cavity) is less dependent upon temperature than is the etch rate of the plug in the cavity. The residues located outside the contact hole also present more exposed surface area for etching than does the contact plug. The lowering of the substrate temperature in the buffer step reduces the etch rate of the conductive plug, permitting careful etchback to the desired plug depth during the second etch step. By leaving the temperature reduced from the buffer step and increasing the amount of ion bombardment of the exposed surface during the second etchback step, it is possible to remove residues from the substrate surface while leaving the plug surface relatively undisturbed. Preferably the ion bombardment is isotropic ion bombardment.
The present invention provides an etchback method which enables the removal of residue of a conductive material from the surface of a substrate, while leaving essentially undisturbed conductive material residing in a cavity within the substrate, despite the presence of an opening to the cavity from the surface of the substrate.